PATMOS 2010 - Grenoble - 7-10 September 2010
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Keynote:

Thursday, 9th, 08:30 - 09:30


Chair: Gilles Sicard, TIMA, France


"3D Integration for Digital & Imagers circuits:
opportunities and challenges"

Dr Marc BELLEVILLE

CEA, LETI, MINATEC.

Abstract

To cope with the market requirements of more functionalities and performances, while keeping reasonable power consumption, the microelectronic industry has always extensively relied on 2D technology scaling. However, with the technical and economic challenges increasing dramatically with the very advanced nodes, 3D integration is now recognized as a very attractive alternative solution to sustain increased system integration. The key drivers towards 3D integration will be first introduced in this talk. Examples of the various 3D process, their associated technological challenges and limitations will be given. At this stage, 3D design rules and 3D specific CAD tools (industrial or at the research level) will be presented and discussed. Then, examples of 3D IPs or circuits will be detailed. Finally, a perspective about another type of 3D integration (stacking transistors instead of dies or wafers) will conclude this talk.

Biography

Marc Belleville received a Phd degree from the Grenoble National Polytechnic Institute in 1980. Since then, he has been involved in circuit design spending the first 6 years in industrial companies. He joined CEA-LETI in 1985, and occupied several positions of team leader. He is now research director and chief scientist of the Architecture, IC Design and Embedded Software division in the Center for Innovation in micro & nanotechnology (MINATEC). Marc Belleville background is mostly focused on the interactions between design and advanced technologies (SOI, heterogeneous or 3D design for instance). He is author or co-author of 18 patents and 50 international communications or publications.

Cable cabine
Grenoble by night
Montains
World Trade Center of Grenoble
IEEE France CEA LETI MINALOGIC TIMA Laboratory Grenoble-INP CNRS UJF-Grenoble