PATMOS 2010 - Grenoble - 7-10 September 2010
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Wednesday, 8th, 09:30 - 10:30

Chair: Laurent Fesquet, TIMA, France

"Variability-Conscious Circuit Designs for
Low-Voltage Memory-Rich Nano-Scale CMOS LSIs"

Dr. Kiyoo ITOH.

Fellow, Central Research Laboratory, Hitachi, Ltd.
1-280 Higashi-Koigakubo, Kokubunji, Tokyo 185-8601, Japan.
Tel: +81-42-323-1111


Low-voltage scaling limitations of nanoscale CMOS LSIs are one of the major problems in the nanoscale era because they cause the evermore-serious power crises with device scaling. The problems stem from two unscalable device parameters: The first is the high value of the lowest necessary threshold voltage Vt (that is, Vt0) of MOSFETs needed to keep the subthreshold leakage low. The second is the variation in Vt (that is, ΔVt), that becomes more prominent in the nanoscale era. The ΔVt caused by the intrinsic random dopant fluctuation is the major source of various ΔVt components. It increases with device scaling and thus intensifies various detrimental effects such as variations in speed and/or the voltage margins of circuits. Due to such inherent features of Vt0 and ΔVt, the operating voltage VDD is facing a 1-V wall in the 65-nm generation, and is expected to rapidly increase with further scaling of bulk MOSFETs, thereby worsening the power crisis. To reduce VDD, the minimum operating voltage Vmin, as determined by Vt0 and ΔVt, must be reduced.
In this talk the Vmin of memory-rich nanoscale CMOS LSIs is investigated in an effort to reduce to below 0.5 V through variability-conscious device and circuit designs. First, Vmin, as a methodology to evaluate the low-voltage potential of MOSFETs, is proposed on the basis of a tolerable speed variation. Second, Vmins of the logic, SRAM, and DRAM blocks are compared, and the SRAM block comprising the six-transistor (6-T) cell turns out to be particularly problematic because it has the highest Vmin. Third, new devices, such as a fully-depleted structure (FD-SOI) and fin-type structure (FinFET) as ΔVt-immune MOSFETs, are investigated to further reduce the Vmins of the above-described blocks. Also investigated are new circuits to reduce Vmin of each block. For example, for the logic block, new dual-Vt0 and dual-VDD dynamic circuits enable the power-delay product to be reduced to 0.09 at a 0.2-V supply owing to gate-source reverse biasing. For the SRAM block, repair techniques, shortening the data line, up-sizing the MOSFETs, control of the common-source line or the word line of the cell, and even the 8-T cell reduce the Vmin. For the DRAM block, if combined with FinFET DRAM cells, a dynamic sense amplifier minimizes the Vt0 and thus Vmin.
Finally, it is concluded that such variability-conscious circuit designs should lead to the achievement of 0.5-V nanoscale LSIs, if relevant devices and fabrication processes are successfully developed.


KIYOO ITOH received the B.S. and Ph.D. Degrees in Electrical Engineering from Tohoku University, Japan, in 1963 and 1976. He is currently a Fellow in Hitachi Ltd. He was a Visiting MacKay Lecturer at U.C. Berkeley in 1994, a Visiting Professor at the University of Waterloo in 1995, and a Consulting Professor at Stanford University in 2000-2001. He served on the IEEE Solid-State Circuits Award Committee from 1998 to 2000. He was a Member of the IEEE Fellow Committee from1999 to 2002, and an elected AdCom Member of IEEE Solid-State Circuits Society from 2001 to 2003. He is an IEEE Solid-State Circuits Society Distinguished Lecturer.
Since 1972 he has led DRAM circuit technology and low-power/low-voltage CMOS circuits at Hitachi Ltd. As the lead designer of the first prototype for eight generations of Hitachi DRAMs ranging from 4Kb to 64Mb, he led the development of world's first DRAM chips, and invented and developed many de-facto standard circuits such as the concept of folded data-line architecture and on-chip voltage down-converters. As early as 1988 as a pioneer, he started to invent and develop subthreshold-current reduction circuits for the standby and active modes, such as power switches, gate-source offset driving, gate-source self-reverse biasing, and dual Vth circuits.
He holds about 440 patents in Japan and US. He has authored and co-authored four books and two book chapters on memory designs, and has given 168 IEEE-related technical papers and presentations. Dr. Itoh has won many honors, including the IEEE Paul Rappaport Award in 1984, the Best Paper Award of ESSCIRC1990, the 1993 IEEE Solid-State Circuits Award (Now named D.O. Pederson Award), and the 2006 IEEE Jun-ichi Nishizawa Medal. He is an IEEE Fellow. In Japan, his awards include a National Medal of Honor with Purple Ribbon.

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