PATMOS 2010 - Grenoble - 7-10 September 2010
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The PATMOS objective is to provide a forum to discuss and investigate emerging challenges in methodologies and tools for the design of upcoming generations of integrated circuits and systems, including reconfigurable hardware such as FPGA's. The technical program will focus on timing, performance and power consumption as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and optimization. The emphasis of the workshop is on, but not limited to, the following topics:

Timing and Performance

  • Methodologies and tools for the analysis, design and verification of timing and performance properties of integrated circuits and systems at all levels of abstraction;
  • Variability and statistical timing analysis;
  • Design for yield, design for manufacturability;
  • Special timing or performance related topics, e.g. crosstalk, synchronization, GALS, side-channel attacks.

Power Dissipation

  • Design techniques for low power circuits and systems at all levels of abstraction;
  • Methods and tools for analysis, characterization, design and optimization of the power consumption;
  • Low power architectures and libraries;
  • Special power related topics, e.g. low voltage, leakage power, power grid, interconnect power, clock tree power, power aware test pattern generation, thermal effects.

Design Experience and Case Studies

  • Examples, test cases, benchmarks or design studies which present innovative solutions for timing, performance or power consumption related design challenges.

Power and Timing Issues Addressing Specific Technologies

  • Reconfigurable Architectures;
  • Caches and Memory Devices;
  • Low Power Software.

Submission: April 5, 2010 Extended to April 19, 2010

Notification of acceptance: May 31, 2010 June 20, 2010

Submission of final version: June 21. 2010 July 4, 2010

Submission guidelines and form: Submission website


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